;buildInfoPackage: chisel3, version: 3.4.1, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit cim_mvm : 
  module cim_rom2 : 
    input clock : Clock
    input reset : Reset
    output io : {flip a : UInt<3>, spo : UInt<8>}
    
    wire mem : UInt<8>[4] @[cim_mvm.scala 24:20]
    mem[0] <= UInt<5>("h012") @[cim_mvm.scala 24:20]
    mem[1] <= UInt<8>("h081") @[cim_mvm.scala 24:20]
    mem[2] <= UInt<8>("h0d1") @[cim_mvm.scala 24:20]
    mem[3] <= UInt<8>("h0ff") @[cim_mvm.scala 24:20]
    node _T = bits(io.a, 1, 0)
    io.spo <= mem[_T] @[cim_mvm.scala 25:10]
    
  module cim_mvm : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip start : UInt<1>, mvm_done : UInt<1>, flip rcil : {row_index : UInt<3>, col_index : UInt<2>, row_length : UInt<3>, col_length : UInt<2>}, flip push_buf : UInt<8>, save_buf : UInt<32>}
    
    reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[cim_mvm.scala 43:22]
    node _T = eq(UInt<2>("h00"), state) @[Conditional.scala 37:30]
    when _T : @[Conditional.scala 40:58]
      node _T_1 = mux(io.start, UInt<2>("h01"), UInt<2>("h00")) @[cim_mvm.scala 45:29]
      state <= _T_1 @[cim_mvm.scala 45:23]
      skip @[Conditional.scala 40:58]
    else : @[Conditional.scala 39:67]
      node _T_2 = eq(UInt<2>("h01"), state) @[Conditional.scala 37:30]
      when _T_2 : @[Conditional.scala 39:67]
        state <= UInt<2>("h02") @[cim_mvm.scala 46:23]
        skip @[Conditional.scala 39:67]
      else : @[Conditional.scala 39:67]
        node _T_3 = eq(UInt<2>("h02"), state) @[Conditional.scala 37:30]
        when _T_3 : @[Conditional.scala 39:67]
          node _T_4 = mux(io.mvm_done, UInt<2>("h00"), UInt<2>("h02")) @[cim_mvm.scala 47:29]
          state <= _T_4 @[cim_mvm.scala 47:23]
          skip @[Conditional.scala 39:67]
    wire input_buf : UInt<2>[4] @[cim_mvm.scala 50:39]
    wire _WIRE : UInt<8>
    _WIRE <= io.push_buf
    node _T_5 = bits(_WIRE, 1, 0) @[cim_mvm.scala 50:39]
    input_buf[0] <= _T_5 @[cim_mvm.scala 50:39]
    node _T_6 = bits(_WIRE, 3, 2) @[cim_mvm.scala 50:39]
    input_buf[1] <= _T_6 @[cim_mvm.scala 50:39]
    node _T_7 = bits(_WIRE, 5, 4) @[cim_mvm.scala 50:39]
    input_buf[2] <= _T_7 @[cim_mvm.scala 50:39]
    node _T_8 = bits(_WIRE, 7, 6) @[cim_mvm.scala 50:39]
    input_buf[3] <= _T_8 @[cim_mvm.scala 50:39]
    wire _WIRE_1 : SInt<16>[2] @[cim_mvm.scala 51:35]
    _WIRE_1[0] <= asSInt(UInt<16>("h00")) @[cim_mvm.scala 51:35]
    _WIRE_1[1] <= asSInt(UInt<16>("h00")) @[cim_mvm.scala 51:35]
    reg output_buf : SInt<16>[2], clock with : (reset => (reset, _WIRE_1)) @[cim_mvm.scala 51:27]
    reg addr : UInt<3>, clock with : (reset => (reset, UInt<1>("h00"))) @[cim_mvm.scala 52:21]
    node _T_9 = eq(state, UInt<2>("h01")) @[cim_mvm.scala 53:14]
    when _T_9 : @[cim_mvm.scala 53:22]
      addr <= io.rcil.row_index @[cim_mvm.scala 54:10]
      skip @[cim_mvm.scala 53:22]
    else : @[cim_mvm.scala 55:26]
      node _T_10 = eq(state, UInt<2>("h02")) @[cim_mvm.scala 55:19]
      when _T_10 : @[cim_mvm.scala 55:26]
        node _T_11 = add(addr, UInt<1>("h01")) @[cim_mvm.scala 56:18]
        node _T_12 = tail(_T_11, 1) @[cim_mvm.scala 56:18]
        addr <= _T_12 @[cim_mvm.scala 56:10]
        skip @[cim_mvm.scala 55:26]
      else : @[cim_mvm.scala 57:14]
        addr <= UInt<1>("h00") @[cim_mvm.scala 58:10]
        skip @[cim_mvm.scala 57:14]
    inst rom of cim_rom2 @[cim_mvm.scala 61:19]
    rom.clock <= clock
    rom.reset <= reset
    rom.io.a <= addr @[cim_mvm.scala 62:12]
    wire rom_out : SInt<4>[2] @[cim_mvm.scala 63:38]
    wire _WIRE_2 : UInt<8>
    _WIRE_2 <= rom.io.spo
    node _T_13 = bits(_WIRE_2, 3, 0) @[cim_mvm.scala 63:38]
    node _T_14 = asSInt(_T_13) @[cim_mvm.scala 63:38]
    rom_out[0] <= _T_14 @[cim_mvm.scala 63:38]
    node _T_15 = bits(_WIRE_2, 7, 4) @[cim_mvm.scala 63:38]
    node _T_16 = asSInt(_T_15) @[cim_mvm.scala 63:38]
    rom_out[1] <= _T_16 @[cim_mvm.scala 63:38]
    wire output_en : UInt<1>[2] @[cim_mvm.scala 64:23]
    wire add_num : SInt<16>[2] @[cim_mvm.scala 65:23]
    node _T_17 = geq(UInt<1>("h00"), io.rcil.col_index) @[cim_mvm.scala 67:27]
    node _T_18 = add(io.rcil.col_index, io.rcil.col_length) @[cim_mvm.scala 67:74]
    node _T_19 = tail(_T_18, 1) @[cim_mvm.scala 67:74]
    node _T_20 = lt(UInt<1>("h00"), _T_19) @[cim_mvm.scala 67:54]
    node _T_21 = and(_T_17, _T_20) @[cim_mvm.scala 67:47]
    output_en[0] <= _T_21 @[cim_mvm.scala 67:18]
    add_num[0] <= rom_out[0] @[cim_mvm.scala 68:16]
    node _T_22 = eq(state, UInt<2>("h01")) @[cim_mvm.scala 69:16]
    when _T_22 : @[cim_mvm.scala 69:24]
      output_buf[0] <= asSInt(UInt<1>("h00")) @[cim_mvm.scala 70:21]
      skip @[cim_mvm.scala 69:24]
    else : @[cim_mvm.scala 71:28]
      node _T_23 = eq(state, UInt<2>("h02")) @[cim_mvm.scala 71:21]
      when _T_23 : @[cim_mvm.scala 71:28]
        node _T_24 = bits(addr, 1, 0)
        node _T_25 = bits(input_buf[_T_24], 1, 1) @[cim_mvm.scala 73:31]
        node _T_26 = bits(_T_25, 0, 0) @[cim_mvm.scala 73:41]
        node _T_27 = sub(asSInt(UInt<1>("h00")), add_num[0]) @[cim_mvm.scala 73:44]
        node _T_28 = tail(_T_27, 1) @[cim_mvm.scala 73:44]
        node _T_29 = asSInt(_T_28) @[cim_mvm.scala 73:44]
        node _T_30 = bits(addr, 1, 0)
        node _T_31 = bits(input_buf[_T_30], 0, 0) @[cim_mvm.scala 74:31]
        node _T_32 = bits(_T_31, 0, 0) @[cim_mvm.scala 74:41]
        node _T_33 = mux(_T_32, add_num[0], asSInt(UInt<1>("h00"))) @[cim_mvm.scala 74:15]
        node _T_34 = mux(_T_26, _T_29, _T_33) @[cim_mvm.scala 73:15]
        node _T_35 = add(output_buf[0], _T_34) @[cim_mvm.scala 72:55]
        node _T_36 = tail(_T_35, 1) @[cim_mvm.scala 72:55]
        node _T_37 = asSInt(_T_36) @[cim_mvm.scala 72:55]
        node _T_38 = mux(output_en[0], _T_37, asSInt(UInt<1>("h00"))) @[cim_mvm.scala 72:28]
        output_buf[0] <= _T_38 @[cim_mvm.scala 72:22]
        skip @[cim_mvm.scala 71:28]
      else : @[cim_mvm.scala 76:29]
        node _T_39 = eq(state, UInt<2>("h00")) @[cim_mvm.scala 76:21]
        when _T_39 : @[cim_mvm.scala 76:29]
          output_buf[0] <= output_buf[0] @[cim_mvm.scala 77:21]
          skip @[cim_mvm.scala 76:29]
    node _T_40 = geq(UInt<1>("h01"), io.rcil.col_index) @[cim_mvm.scala 67:27]
    node _T_41 = add(io.rcil.col_index, io.rcil.col_length) @[cim_mvm.scala 67:74]
    node _T_42 = tail(_T_41, 1) @[cim_mvm.scala 67:74]
    node _T_43 = lt(UInt<1>("h01"), _T_42) @[cim_mvm.scala 67:54]
    node _T_44 = and(_T_40, _T_43) @[cim_mvm.scala 67:47]
    output_en[1] <= _T_44 @[cim_mvm.scala 67:18]
    add_num[1] <= rom_out[1] @[cim_mvm.scala 68:16]
    node _T_45 = eq(state, UInt<2>("h01")) @[cim_mvm.scala 69:16]
    when _T_45 : @[cim_mvm.scala 69:24]
      output_buf[1] <= asSInt(UInt<1>("h00")) @[cim_mvm.scala 70:21]
      skip @[cim_mvm.scala 69:24]
    else : @[cim_mvm.scala 71:28]
      node _T_46 = eq(state, UInt<2>("h02")) @[cim_mvm.scala 71:21]
      when _T_46 : @[cim_mvm.scala 71:28]
        node _T_47 = bits(addr, 1, 0)
        node _T_48 = bits(input_buf[_T_47], 1, 1) @[cim_mvm.scala 73:31]
        node _T_49 = bits(_T_48, 0, 0) @[cim_mvm.scala 73:41]
        node _T_50 = sub(asSInt(UInt<1>("h00")), add_num[1]) @[cim_mvm.scala 73:44]
        node _T_51 = tail(_T_50, 1) @[cim_mvm.scala 73:44]
        node _T_52 = asSInt(_T_51) @[cim_mvm.scala 73:44]
        node _T_53 = bits(addr, 1, 0)
        node _T_54 = bits(input_buf[_T_53], 0, 0) @[cim_mvm.scala 74:31]
        node _T_55 = bits(_T_54, 0, 0) @[cim_mvm.scala 74:41]
        node _T_56 = mux(_T_55, add_num[1], asSInt(UInt<1>("h00"))) @[cim_mvm.scala 74:15]
        node _T_57 = mux(_T_49, _T_52, _T_56) @[cim_mvm.scala 73:15]
        node _T_58 = add(output_buf[1], _T_57) @[cim_mvm.scala 72:55]
        node _T_59 = tail(_T_58, 1) @[cim_mvm.scala 72:55]
        node _T_60 = asSInt(_T_59) @[cim_mvm.scala 72:55]
        node _T_61 = mux(output_en[1], _T_60, asSInt(UInt<1>("h00"))) @[cim_mvm.scala 72:28]
        output_buf[1] <= _T_61 @[cim_mvm.scala 72:22]
        skip @[cim_mvm.scala 71:28]
      else : @[cim_mvm.scala 76:29]
        node _T_62 = eq(state, UInt<2>("h00")) @[cim_mvm.scala 76:21]
        when _T_62 : @[cim_mvm.scala 76:29]
          output_buf[1] <= output_buf[1] @[cim_mvm.scala 77:21]
          skip @[cim_mvm.scala 76:29]
    node lo = asUInt(output_buf[0]) @[cim_mvm.scala 80:35]
    node hi = asUInt(output_buf[1]) @[cim_mvm.scala 80:35]
    node _T_63 = cat(hi, lo) @[cim_mvm.scala 80:35]
    io.save_buf <= _T_63 @[cim_mvm.scala 80:15]
    node _T_64 = add(io.rcil.row_index, io.rcil.row_length) @[cim_mvm.scala 81:46]
    node _T_65 = tail(_T_64, 1) @[cim_mvm.scala 81:46]
    node _T_66 = sub(_T_65, UInt<1>("h01")) @[cim_mvm.scala 81:66]
    node _T_67 = tail(_T_66, 1) @[cim_mvm.scala 81:66]
    node _T_68 = eq(addr, _T_67) @[cim_mvm.scala 81:24]
    io.mvm_done <= _T_68 @[cim_mvm.scala 81:15]
    
